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Delhi

Active Inductor Design

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Published in: Physics
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Active Inductor Design using CMOS

Najeemullah B / Hyderabad

8 years of teaching experience

Qualification: M.Tech (Moguls Institute of learning - 2007)

Teaches: Algebra, Computer Science, Mathematics, Physics, B.Tech Tuition, Electronics, M.Tech Tuition, Railways Exams, RRB, Sub-Inspector Exam, UGC Exams, Chemical, Electrical, Embedded Systems, Hardware Training, Informatica, MCA Subjects

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  1. ACTIVE INDUCTOR Design and Analysis NAJEEMULLA BAIG 1
  2. Objective of The Research The objectives of this research are listed below: a To study and analyze the performance of active inductor a To design and analyze performance of Complementary Metal Oxide Semiconductor (CMOS) PA with On-Chip active inductor. Design is based on 0.18um CMOS process. 2
  3. Applications of CMOS spiral inductors and transformers CMOS spiral inductors and transformers have found a broad range of applications in Ohigh-speed analog signal processing including impedance matching and gain-boosting in wireless transceivers, Obandwidth improvement in broadband data communications over wire and optical channels, aoscillators and modulators, ORF band pass filters, RF phase shifters, RF power dividers, and acoupling of high-frequency signals, to name a few. 3
  4. RF Receiver Antenna BPFI LNA BPF2 Mixer BPF3 IF Amp: RF front end 2VFl + total NF3-1 .4v2 Demodulator 1 .Q4vn 1
  5. Limitations of Passive inductors passive inductors such as spiral and bonding wire have been widely used by designers. But at high frequencies, series resistance due to skin effect causes series losses and magnetic current of the inductor induces eddy currents in the substrate which results in substrate losses. This leads to reduction of Q-factor. In planar spiral inductors the inductance is directly proportional to the number of turns of the coil. This limits the inductance value. uon2r L= Fig. I 5 Typical layout of a spiral inductor using two rtrtal layers
  6. While the inductance of stacked inductors increases linearly with the increase in the number of spiral layers, the self resonant frequency of inductor decreases in a non-linear fashion. There is also an existence of parasitic capacitance between spiral layers. So in order to overcome the limitations of passive inductors such as low Q-factor, low self resonant frequency, small and non tunable inductance and large active inductors are preferred area, Fig.2 Stacked inductors 6
  7. Active Inductor Motivation a The main motivation to implement active inductor is to avoid using passive inductor such as spiral and bonding wire inductor in the design. a They require large die area and have a fixed and low Q-factor value since CMOS provides a low resistive substrate. a More over, passive inductor tends to give a single-band operation for the design since it has a fixed inductance value QActive inductors can also achieve multi-band operation. alts capability to tune and switch the inductance value has made them more reliable to use. Furthermore, Q-factor value can be tuned to achieve the design specification 7
  8. Active Inductor Motivation (contd..) QEven though we can have smaller die area and programmable capability, we need to pay their trade off by introducing a higher noise and power consumption in our design. a Therefore, a good consideration needs to be made to make sure our design performance can be achieved with active inductor as an alternative to avoid passive inductor. 8
  9. Active Inductor Architecture Active inductor is designed by using the gyrator-C topology to provide the inductance. Gyrator-C is developed by using two amplifiers which are connected back-to-back. This topology is capable of transforming the intrinsic capacitance from the amplifier to an inductive behavior. Iin ....1..........................> c 2 Fig.3 Basic Gyrator-C Topology 9
  10. in 2 Gm2 VI Fig.4 Small signal equivalent circuit ml m2 ml 7712 Gyrator-C networks can therefore be used to synthesize inductors. 10
  11. 3 g ml gm2 QBased on Equation 3, it shows that we can tune the inductance value by tuning the gml and gm2 rather than tuning C2 as its value are fixed by the length and width of the transistors. a To increase the inductance value, we need to decrease the current as this will decrease gml and gm2. a Therefore, to have smaller inductance value, a higher current need to be supplied to increase gml and gm2. 11
  12. g ml gm2 qc, 4 a The same method can be applied to increase the fr by referring to Equation 4. a This will increase power consumption of the design if smaller inductance value and higher resonant frequency are required. 12
  13. Single ended Lossy Gyrator-C Fig.5 Write KCL at node 1 and 2 (SCI + G G V =0 01 1 — ml 2 v 1 o At node 1 in At node 2 02 2 in 13
  14. The admittance looking into port2 of the gyrator-C network is obtained from ml m2 ml m2 02 ml m2 ml m2 6 14
  15. Basic active inductor Ml and M2 are amplifier 1 and amplifier2 respectively. The parasitic capacitance of both transistors will provide Cl and C2 to this circuit. However, this architecture has limited Q- factor values the output as transconductance at VI is quite big. Fig. 7 dd I dc Fig.6 Circuit of Basic Active Inductor 15
  16. Active inductor design: Using equation no.8 g ml m2 16.9nH gs4 g ml g m3 cgs = CGS0.w +0.67WLC ox let...Cgs4 = 200fF 200fF = 11.93g g ml m3 16.9nH 1 let...gml = = 3.453mQ we...have WI = W3 = 72.4gm ForM4 200fF = W[2.4p + W = 0.359mm 16
  17. •r uoso ools Window ayou ul e Assura Elace Help Workspace: Classic n ayou x:-67a.a5üü v:laa.asoo dX:-1ü73.755ü dY:aa.735ü Oist:1ü77.Z5Z4 23. Fig.8 Comparison between Passive Spiral Inductor layout and active inductor
  18. Power amplifier Design for NAVIC application using active inductor TRANSCEIVER TX UP-MIXER DAC TX LO DC RX DOWN-MIXER POWER AMPLIFIER Transmit leakage RX VARIABLE GAIN AMPLIFIER RF BANDPASS FILTER BANK Fig.9 Transceiver block diagram 18
  19. QI-.lerieS? 19

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