Looking for a Tutor Near You?

Post Learning Requirement »
x

Choose Country Code

x

Direction

x

Ask a Question

x

Hire a Tutor
Delhi

Digital Electronics Nand NOR Equivalents And Xor Implementations

Loading...

Published in: Electronics
5,053 Views

This tutorial discusses about the implementation of AND-OR circuits in terms of NAND NAND representations and OR-AND circuits in terms of NOR-NOR representation. It discusses optimisation methods for doing the same.It then elaborates about Odd and Even functions, discusses the concept of parity generators and parity checkers, Buffers, High impedance outputs, three state buffers and wired output for resolution of output values.

Parag P / Indore

10 years of teaching experience

Qualification: M. Tech. Embedded Systems

Teaches: Algebra, Mathematics, Physics, Statistics, Electronics

Contact this Tutor
  1. Digital Electronics Presentation on Lecture 8 : NAND and XOR Implementations Presented By : Parag Parandkar
  2. Acknowledgement The presenter would like to thank and acknowledge for the adoption of slides from Electrical and Computer engineering , university of Massachusetts Amherst. The presenter would also like to thank and acknowledge for the adoption of slides from Logic and Computer Design fundamentals 4th Edition by Charles Kime and Thomas for 2008 Pearson Education limited. > The copyrights belongs to the original author. The presentation is being used for educational and non commercial purpose.
  3. Contents Other gate types. Why ? NAND & NOR : Universal gates AND-OR -Y NAND-NAND I OR-AND -Y NOR-NOR Conversion between forms Exclusive-OR and Exclusive-NOR circuits Uses of XOR / XNOR XOR Implementations XOR-XNOR identities Odd and Even functions Parity generators and checkers Buffer High Impedance Output 3 state buffer Wired Output : resolving output value
  4. Other Gate Types Why? — Low cost implementation — Useful in implementing Boolean functions — Convenient conceptual representation ' Gate classifications — Primitive gate - a gate that can be described using a single primitive operation type (AND or OR) plus optional inversion(s). — Complex gate - a gate that requires more than one primitive operation type for its description Primitive gates will be covered first
  5. NAND Gate The basic NAND gate has the following symbol and truth table: - AND-Invert (NAND) Symbol: X Y NAND 01 1 NAND represents NOT AND. The small "bubble" circle represents the invert function The NAND gate is implemented efficiently in CMOS technology in terms of chip area and speed
  6. NAND Gate: Invert-OR Symbol Applying DeMorgan's Law: Invert-OR = NAND x X Y = NAND This NAND symbol is called Invert-OR — Since inputs are inverted and then ORed together AND-Invert & Invert-OR both represent NAND gate — Having both makes visualization of circuit function easier Unlike AND, the NAND operation is NOT associative (X NAND Y) NAND Z # X NAND (Y NAND Z)
  7. The NAND Gate is Universal NAND gates can implement any Boolean function NAND gates can be used as inverters, or to implement AND / OR operations A NAND gate with one input is an inverter AND is equivalent to NAND with inverted output OR is equivalent to NAND with inverted inputs x x X X+Y
  8. NOR Gate The basic NOR gate has the following symbol and truth table: - OR-invert (NOR) Symbol: x X Y NOR 001 NOR represents NOT OR. The small "bubble" circle represents the invert function. The NOR gate is also implemented efficiently in CMOS technology in terms of chip area and speed
  9. NOR Gate: Invert-AND Symbol The Invert-AND symbol is also used for NOR x X, NOR This NOR symbol is called Invert-AND, since inputs are inverted and then ANDed together OR-Invert & Invert-AND both represent NOR gate — Having both makes visualization of circuit function easier ' Unlike OR, the NOR operation is NOT associative (X NOR Y) NOR Z # X NOR (Y NOR Z)
  10. The NOR Gate is also Universal NOR gates can implement any Boolean function NOR gates can be used as inverters, or to implement AND / OR operations A NOR gate with one input is an inverter OR is equivalent to NOR with inverted output AND is equivalent to NOR with inverted inputs x x
  11. NAND-NAND & NOR-NOR Networks DeMorgan's Law: push bubbles or introduce in pairs or remove pairs.
  12. NAND-NAND Networks Mapping from AND/OR to NAND/NAND
  13. Implementations of Two-level Logic Sum-of-products — AND gates to form product terms (minterms) — OR gate to form sum ' Product-of-sums — OR gates to form sum terms (maxterms) — AND gates to form product
  14. Two-level Logic using NAND Gates ' Replace minterm AND gates with NAND gates Place compensating inversion at inputs of OR gate
  15. Two-level Logic using NAND Gates (cont'd) OR gate with inverted inputs is a NAND gate - de Morgan's: A' + B' = (A, B)' Two-level NAND-NAND network — Inverted inputs are not counted — In a typical circuit, inversion is done once and signal distributed
  16. Conversion Between Forms Convert from networks of ANDs and ORS to networks of NANDs and NORs — Introduce appropriate inversions ("bubbles") Each introduced "bubble" must be matched by a corresponding "bubble" Conservation of inversions — Do not alter logic function Example: AND/OR to NAND/NAND NAND z NAN z NAND
  17. Conversion Between Forms (cont' d) ' Example: verify equivalence of two forms z c NAND NAND NAN z
  18. Conversion to NAND Gates ' Start with SOP (Sum of Products) — circle Is in K-maps ' Find network of OR and AND gates c (a) AND OR network Bubbles cancel c D (b) First step in NAND conversion F B' dded inverter c D' (c) Completed conversion dded inverter F E'
  19. Multi-level Logic x = AD F +AEF+BDF+BEF+CDF+CEF+G — Reduced sum-of-products form — already simplified — 6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!) — 25 wires (19 literals plus 6 internal wires) — Factored form — not written as two-level S-o-P — 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate — 10 wires (7 literals plus 3 internal wires) x
  20. Conversion of Multi-level Logic to NAND Gates Level 1 Level 2 Level 3 Level 4 original AND-OR network introduction and conservation of bubbles redrawn in terms of conventional NAND gates c B'
  21. Conversion Between Forms ' Example (a) Original circuit (c) Distribute bubbles some mismatches Add double bubbles at inputs Insert inverters to fix mismatches (b) (d)
  22. Exclusive-OR and Exclusive-NOR Circuits Exclusive-OR (XOR) produces a HIGH output whenever the two inputs are at opposite levels. AB AB (a) XOR gate symbols (b) A o x=AB+AB B o x x = AOB (c)
  23. Exclusive-NOR Circuits Exclusive-NOR (XNOR) : Exclusive-NOR (XNOR) produces a HIGH output whenever the two inputs are at the same level. x x = AB +AB XNOR gate symbols (b) x=AOB (c)
  24. Exclusive-NOR Circuits XNOR gate may be used to simplify circuit implementation. c 3 c D ABCD ABCD ÄD (a) AD(B O C) BOC z = ABCD + ABCD +AD z = AD (B o C) +-ÄD (b)
  25. XOR Function XOR function can also be implemented with AND/OR gates (also NANDs). (a) With AND-OR-NOT gates (b) With NAND gates Exclusive OR Implementations
  26. Even function Odd function BC XOR Function even number of inputs are 1. odd number of inputs are 1. 01 11 10 BC oo 01 11 10 (a) Odd function F = A 9 BOC Map of 3-variable Exclusive-OR function (a) Even function
  27. Uses for XOR / XNOR SOP Expressions for XOR/XNOR: - The XOR function is: X CY = X Y + X Y — The eXclusive NOR (XNOR) function, know also as equivalence is: Uses for the XOR and XNORs gate include: — Adders/subtractors/multipliers — Counters/incrementers/decrementers — Parity generators/checkers Strictly speaking, XOR and XNOR gates do no exist for more that two inputs. Instead, they are replaced by odd and even functions.
  28. XOR Implementations SOP implementation for XOR: XO Y = X y-+X-y x NAND only implementation for XOR: x
  29. x ox XOR / XNOR Identities x 01=r x cr=l (X OY)OZ = X (7öV)0z = x XOR and XNOR are associative operations Additional Gates and Circuits — 29
  30. Odd Function The XOR function can be extended to 3 or more variables For 3 or more variables, XOR is called an odd function The function is I if the total number of I 's in the inputs is odd X OY OZ -r V Z +XYä+XVä+XYZ YZ oo 01 11 10 x X CYO Z YZ oo 01 11 10 wx 11 WCXCYCZ
  31. Odd and Even Functions The Is of an odd function correspond to inputs with an odd number of Is The complement of an odd function is called an even function The Is of an even function correspond to inputs with an even number of Is ' Implementation of odd and even functions use trees made up of 2-input XOR or XNOR gates
  32. Odd/Even Function Implementation Design a 3-input odd function with 2-input XOR: 3-input odd function: x z Design a 4-input even function with 2-input XOR and XNOR gates: 4-input even function:
  33. Parity Generators and Checkers A parity bit added to n-bit code produces (n+l)-bit code with an odd (or even) count of Is Odd Parity bit: count of Is in (n+l)-bit code is odd — So use an even function to generate the odd parity bit Even Parity bit: count of Is in (n+l)-bit code is even — So use an odd function to generate the even parity bit ' To check for odd parity — Use an even function to check the (n+l)-bit code ' To check for even parity — Use an odd function to check the (n+l)-bit code
  34. Parity Generator & Checkers n-bit code Parity Generator Sender (n+l)-bit code Parity Error Checker Receiver Design an even parity generator and checker for 3-bit codes Solution: Use 3-bit odd function to generate even parity bit Use 4-bit odd function to check for errors in even parity codes Operation: = gives = and E = O If Y changes from 0 to 1 between x z x z generator and checker, then E = 1 indicates an error
  35. Parity Generation and Checking XOR gates used to implement the parity generator and the parity checker for an even-parity system. Original data From D3 Even-parity generator nnD (a) Even-parity checker (b) Parity (P) Transmitted data with parity bit Error (E) {l = error O = no error) transmitter DO
  36. Buffer A buffer is a gate with the function F = X x ' In terms of Boolean function, 11 a buffer is the same as a connection! ' So why use it? — A buffer is used to amplify an input signal — Permits more gates to be attached to output — Also, increases the speed of circuit operation
  37. Hi-Impedance Output ' Logic gates introduced thus far — Have 1 and 0 output values — Cannot have their outputs connected together Three-state logic adds a third logic value: — Hi-Impedance output: Hi-Z What is Hi-Impedance output? — The output appears to be disconnected from the input — Behaves as an open circuit between gate input & output Hi-Z state makes a gate output behave differently: — Three output values: 1, 0, and Hi-Z — Hi-impedance gates can connect their outputs together
  38. The 3-State Buffer IN = data input EN = Enable control input OUT = data output If EN = O then OUT = HI-Z — Regardless of the value on IN Output disconnected from input If EN = 1, then OUT -IN Output follows the input value Variations: EN can be inverted OUT can be inverted — By addition of bubbles to signals IN Symbol OUT Truth Table o 1 1 IN x O 1 OUT Hi-Z O 1
  39. Wired Output: Resolving Output Value The output of 3-state buffers can be wired together At most one 3-state buffer can be enabled. Resolved output is equal to the output of the enabled 3-state buffer If multiple 3-state buffers are enabled at the same time then conflicting outputs will burn the circuit ENO oo INO ENI 01 INI EN2 02 IN2 Resolution Table OUT oo 0 or 1 Hi-Z Hi-Z Hi-Z 0 or 1 01 Hi-Z 0 or 1 Hi-Z Hi-Z 0 or 1 02 Hi-Z Hi-Z 0 or 1 Hi-Z 0 or 1 OUT oo 01 02 Hi-Z Burn
  40. Terms of Use All (or portions) of this material 0 2008 by Pearson Education, Inc. Permission is given to incorporate this material or adaptations thereof into classroom presentations and handouts to instructors in courses adopting the latest edition of Logic and Computer Design Fundamentals as the course textbook. These materials or adaptations thereof are not to be sold or otherwise offered for consideration. This Terms of Use slide or page is to be included within the original materials or any adaptations thereof.

Need a Tutor or Coaching Class?

Post an enquiry and get instant responses from qualified and experienced tutors.

Post Requirement

Related PPTs

Upload PPTs

If you have your own PowerPoint Presentations which you think can benefit others, please upload on LearnPick. For each approved PPT you will get 100 Credit Points and 100 Activity Score which will increase your profile visibility.

Upload Now
Home > PowerPoint Slides > Digital Electronics Nand NOR Equivalents And Xor Implementations